VHDL-2019 example of conversion from integer to std_logic_vector on EDA Playground. So when constructing things like this, I don't need to look it up, I just think about how I'm changing the data. These don't have a length argument because both sides are already the same. "Take these bits and stuff them in this type, no modifications required". The functions without to_ (straight std_logic_vector(.) in this example) are used when types are directly compatible already. This is why to_unsigned requires you to specify the length. They make them unsigned or a certain length or both. Knowing why this method works and is recommended is one step closer to thinking about what you're writing in hardware terms.īonus tip: functions prefixed by to_ are ones that shorten/change the operands.
#UNSINGED INTEGER TO BINARY CONVERTER CODE#
But in VHDL the code you write has physical implications in hardware. When coming from a traditional programming background, it's very easy to get stuck in a programming way of thinking. That's this part: tounsigned(myint, myslv'length)) 'I have this integer, I want it to be unsigned, and I want it to fit into the length of my SLV.' Stage 2: Then, take those bits and use them to drive the myslv. Stage 1: Make my integer shorter, and unsigned. A <= B in VHDL is read out loud as "A is driven by B")Ĭombined, this gets you: my_slv <= std_logic_vector(to_unsigned(my_int, my_slv'length)) An integer is signed, and usually 32 bits (if i remember correctly). "Take these bits, and use them to drive my slv" Stage 2: Then, take those bits and use them to drive the my_slv. "I have this integer, I want it to be unsigned, and I want it to fit That's this part: to_unsigned(my_int, my_slv'length)) How many bits? Well, how long is your SLV?Īn integer is signed, and usually 32 bits (if i remember correctly). Is it signed or unsigned? Ths SLV doesn't know or care. It comes down to how these types are viewed by the tools.Ī standard_logic_vector is literally a bunch of 1s or 0s. However, I would like to elaborate about why this is recommended, and why VHDL has such a seemingly convoluted way of converting integers into std_logic_vectors. My_slv <= std_logic_vector(to_unsigned(my_int, my_slv'length)) As the main answer says, the recommended method is as follows: use ieee.numeric_std.all